1 ps8552d 02/24/05 features ? cmos technology for bus and analog applications low on resistance: 8-ohms at 3.0v wide v cc range: 1.65v to 5.5v rail-to-rail signal range control input overvoltage tolerance: 5.5v min. fast transition speed: 5.2ns max. at 5v high off isolation: 57db at 10mhz 54db (10mhz) crosstalk rejection reduces signal distortion break-before-make switching high bandwidth: 250 mhz extended industrial temperature range: ?40 c to 85 c improved direct replacement for nc7sb3157 packaging (pb-free & green available): - 6-pin tdfn (za) - 6-pin sc70 (c) applications cell phones pdas portable instrumentation battery powered communications computer peripherals pi5a3157 sot iny tm low voltage spdt analog switch 2:1 mux/demux bus switch 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 the pi5a3157 is a high-bandwidth, fast single-pole double-throw (spdt) cmos switch. it can be used as an analog switch or as a low-delay bus switch. specified over a wide operating power supply voltage range, 1.65v to 5.5v, the pi5a3157 has a maximum on resistance of 12-ohms at 1.65v, 9-ohms at 2.3v & 6-ohms at 4.5v. break-before-make switching prevents both switches being enabled simultaneously. this eliminates signal disruption during switching. the control input, s, tolerates input drive signals up to 5.5v, independent of supply voltage. pi5a3157 is an improved direct replacement for the nc7sb3157. ) s ( t u p n i c i g o ln o i t c n u f 0b 0 a o t d e t c e n n o c 1b 1 a o t d e t c e n n o c logic function table n i p r e b m u n e m a nn o i t p i r c s e d 11 bt r o p a t a d 2d n gd n u o r g 30 b) d e s o l c y l l a m r o n ( t r o p a t a d 4a t r o p a t a d / t u p t u o n o m m o c 5v c c y l p p u s r e w o p e v i t i s o p 6s l o r t n o c c i g o l pin description connection diagram b 1 gnd 1 2 3 6 4 b 0 s 5v cc a
2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi5a3157 sot iny tm low voltage spdt analog switch 2:1 mux/demux bus switch ps8552d 02/24/05 recommended operating conditions (3) supply voltage operating (v cc ) . . . . . . . . . . . . . . 1.65v to 5.5v control input voltage (v in ) . . . . . . . . . . . . . . . . . . . . 0v to v cc switch input voltage (v in ) . . . . . . . . . . . . . . . . . . . . . 0v to v cc output voltage (v out ) . . . . . . . . . . . . . . . . . . . . . . . . 0v to v cc operating temperature (t a ) . . . . . . . . . . . . . . . ?40c to +85c input rise and fall time (t r ,t f ) control input v cc = 2.3v - 3.6v . . . . . . . . . . 0ns/v to 10ns/v control input v cc = 4.5v - 5.5v . . . . . . . . . . . 0ns/v to 5ns/v thermal resistance ( ja ) . . . . . . . . . . . . . . . . . . . . . . 350c/w absolute maximum ratings (1) supply voltage v cc ................................................ ?0.5v to +7v dc switch voltage (v s ) (2) ............................. ?0.5v to v cc +0.5v dc input voltage (v in ) (2) .................................... ?0.5v to +7.0v dc output current (v out ) ............................................... 128ma dc v cc or ground current (i cc /i gnd ) ............................ 100ma storage temperature range (t stg ) ................ ?65c to +150c junction temperature under bias (t j ) ............................... 1 50c junction lead temperature (t l ) (soldering, 10 seconds) ................................................ 2 60c power dissipation (p d ) @ +85c ..................................... 180mw notes 1. absolute maximum ratings? may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. 2. the input and output negative voltage ratings may be exceeded if the inut and output diode current ratings are observed. 3. control input must be held high or low; it must not float. r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e te g a t l o v y l p p u s) c o ( p m e t. n i mp y t. x a m s t i n u v r a i t u p n i g o l a n a e g n a r l a n g i s v c c t a & c 5 2 = c 5 8 o t c 0 4 ? 0v c c v r n o n o e c n a t s i s e r ) 4 ( i o v , a m 0 3 = n i v 0 = v 5 . 4t a c 5 2 = 46 ? i o v , a m 0 3 ? = n i v 4 . 2 =58 i o v , a m 0 3 ? = n i v 5 . 4 =83 1 r n o i o v , a m 0 3 = n i v 0 = v 5 . 4 t a c 0 4 ? = c 5 8 o t 6 i o v , a m 0 3 ? = n i v 4 . 2 =8 i o v , a m 0 3 ? = n i v 5 . 4 =3 1 r n o i o v , a m 4 2 = n i v 0 = v 0 . 3t a c 5 2 = 58 i o v , a m 4 2 ? = n i v 0 . 3 =2 19 1 r n o i o v , a m 4 2 = n i v 0 = v 0 . 3 t a c 0 4 ? = c 5 8 o t 8 i o v , a m 4 2 ? = n i v 0 . 3 =9 1 r n o i o v , a m 8 = n i v 0 = v 3 . 2t a c 5 2 = 69 i o v , a m 8 ? = n i v 3 . 2 =6 14 2 r n o i o v , a m 0 3 = n i v 0 = v 3 . 2 t a c 0 4 ? = c 5 8 o t 9 i o v , a m 0 3 ? = n i v 4 . 2 =4 2 r n o i o v , a m 4 = n i v 0 = v 5 6 . 1t a c 5 2 = 82 1 i o v , a m 4 ? = n i v 5 6 . 1 =7 29 3 r n o i o v , a m 4 = n i v 0 = v 5 6 . 1 t a c 0 4 ? = c 5 8 o t 2 1 i o v , a m 4 ? = n i v 5 6 . 1 =9 3 dc electrical characteristics (over the operating temperature range, t a = ?40c to 85c)
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 3 ps8552d 02/24/05 pi5a3157 sot iny tm low voltage spdt analog switch 2:1 mux/demux bus switch r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e te g a t l o v y l p p u s) c o ( p m e t. n i mp y t. x a m s t i n u ? r n o n o e c n a t s i s e r h c t a m n e e w t e b s l e n n a h c ) 6 , 5 , 4 ( i a v , a m 0 3 ? = n b = v 5 1 . 3 v 5 . 4 t a c 5 2 = 5 1 . 0 ? i a v , a m 4 2 ? = n b v 1 . 2 =v 0 . 32 . 0 i a v , a m 8 ? = n b v 6 . 1 =v 3 . 23 . 0 i a v , a m 4 ? = n b v 5 1 . 1 =v 5 6 . 13 . 0 r f n o n o e c n a t s i s e r s s e n t a l f ) 7 , 5 , 4 ( i a , a m 0 3 ? = 0 v n b v c c v 0 . 5 t a c 5 2 = 6 ? i a , a m 4 2 ? = 0 v n b v c c v 3 . 32 1 i a 0 , a m 8 ? = v n b v c c v 5 . 22 2 i a 0 , a m 4 ? = v n b v c c v 8 . 10 9 v h i h g i h t u p n i e g a t l o v l e v e l h g i h c i g o l v c c v 5 9 . 1 o t v 5 6 . 1 = t a c 5 2 = c 0 4 ? & c 5 8 o t v 5 7 . 0 c c v v c c v 5 . 5 o t v 3 . 2 =v 7 . 0 c c v l i w o l t u p n i e g a t l o v l e v e l w o l c i g o l v c c v 5 9 . 1 o t v 5 6 . 1 =v 5 2 . 0 c c v v c c v 5 . 5 o t v 3 . 2 =v 5 2 . 0 c c t u p n i e g a k a e l t n e r r u c 0 v n i 5 . 5 vv c c v 5 . 5 o t v 0 = t a c 5 2 =1 . 0 a t a c 0 4 ? = c 5 8 o t 0 . 1 i f f o e t a t s f f o e g a k a e l t n e r r u c 0 v n i v 5 . 5v c c v 5 . 5 o t v 5 6 . 1 = t a c 5 2 =1 . 0 t a c 0 4 ? = c 5 8 o t 0 1 i c c t n e c s e i u q y l p p u s t n e r r u c , f f o r o n o s l e n n a h c l l a v n i v = c c , d n g r o i t u o 0 = v c c v 5 . 5 = t a c 5 2 =1 t a c 0 4 ? = c 5 8 o t 0 1 dc electrical characteristics (over the operating temperature range, t a = ?40c to 85c) (continued) notes: 4. measured by voltage drop between a and b pins at the indicated current through the device. on resistance is determined by the lower of the voltages on two ports (a or b). 5. parameter is characterized but not tested in production. 6. dr on = r on max ? r on min. measured at identical v cc , temperature and voltage levels. 7. flatness is defined as difference between maximum and minimum value of on resistance over the specified range of conditions. 8. guaranteed by design. r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e te g a t l o v y l p p u s) c o ( p m e t. n i mp y t. x a m s t i n u c n i t u p n i l o r t n o c v c c v 0 . 5 =t a c 5 2 = 3 . 2 pf c b - o i f f o h c t i w s , t r o p b r o f z h m 1 = f ) 2 1 ( 5 . 6 c n o - a o i n o h c t i w s , t r o p a r o f 5 . 8 1 capacitance (12)
4 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi5a3157 sot iny tm low voltage spdt analog switch 2:1 mux/demux bus switch ps8552d 02/24/05 r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t y l p p u s e g a t l o v ) c o ( p m e t. n i mp y t. x a ms t i n u t h l p t l h p n o i t a g a p o r p : y a l e d n b o t a t i u c r i c t s e t e e s . 2 d n a 1 s m a r g a i d v i n e p o ) 0 1 ( v c c v 7 . 2 o t v 3 . 2 = t a & c 5 2 = c 5 8 o t 0 4 ? 2 . 1 s n v c c v 6 . 3 o t v 0 . 3 =8 . 0 v c c v 5 . 5 o t v 5 . 4 =3 . 0 t l z p t h z p t u p t u o n r u t e l b a n e : e m i t n o n b o t a t i u c r i c t s e t e e s . 2 & 1 s m a r g a i d v i v 2 = c c t r o f l z p , v i t r o f v 0 = h z p v c c v 5 9 . 1 o t v 5 6 . 1 = t a c 5 2 = 73 2 v c c v 7 . 2 o t v 3 . 2 =5 . 33 1 v c c v 6 . 3 o t v 0 . 3 =5 . 29 . 6 v c c v 5 . 5 o t v 5 . 4 =7 . 12 . 5 t l z p t h z p o utput e nable t urn n ot ime : a to b n t i u c r i c t s e t e e s . 2 d n a 1 s m a r g a i d v i v 2 = c c t r o f l z p , v i t r o f v 0 = h z p v c c v 5 . 2 = t a & c 5 2 = c 5 8 o t 0 4 ? 4 2 v c c v 3 . 3 =4 1 v c c v 6 . 3 o t v 0 . 3 =6 . 7 v c c v 5 . 5 o t v 5 . 4 =7 . 5 t z l p t z h p t u p t u o n r u t e l b a s i d : e m i t f f o n b o t a t i u c r i c t s e t e e s . 2 d n a 1 s m a r g a i d v i v 2 = c c t r o f l z p , v i t r o f v 0 = h z p v c c v 5 9 . 1 o t v 5 6 . 1 = t a c 5 2 = 35 . 2 1 v c c v 7 . 2 o t v 3 . 2 =27 v c c v 6 . 3 o t v 0 . 3 =5 . 15 v c c v 5 . 5 o t v 5 . 4 =8 . 05 . 3 t z l p t z h p t u p t u o n r u t e l b a s i d : e m i t f f o n b o t a t i u c r i c t s e t e e s . 2 d n a 1 s m a r g a i d v i v 2 = c c t r o f l z p , v i t r o f v 0 = h z p v c c v 5 . 2 = t a o t 0 4 ? = c 5 8 3 1 v c c v 3 . 3 =5 . 7 v c c v 6 . 3 o t v 0 . 3 =3 . 5 v c c v 5 . 5 o t v 5 . 4 =8 . 3 t m b e r o f e b k a e r b e m i t e k a m t i u c r i c t s e t e e s . 9 m a r g a i d ) 9 ( v c c v 5 . 2 = t a & c 5 2 = c 5 8 o t 0 4 ? 5 . 0 v c c v 3 . 3 =5 . 0 v c c v 6 . 3 o t v 0 . 3 =5 . 0 v c c v 5 . 5 o t v 5 . 4 =5 . 0 q e g r a h c n o i t c e j n i c l v , f n 1 . 0 = n e g , v 0 = r n e g 0 = ? . 4 t i u c r i c t s e t e e s . v c c v 0 . 5 = t a c 5 2 = 7 c p v c c v 3 . 3 =3 r r i on o i t a l o s i f f o r l 0 5 = ? v , n e g , v 0 = r n e g 0 = ? . . 5 t i u c r i c t s e t e e s ) 1 1 ( v c c v 5 . 5 o t v 5 6 . 1 =t a c 5 2 =7 5 ? b d x k l a t k l a t s s o r c n o i t a l o s i . 6 t i u c r i c t s e t e e sv c c v 5 . 5 o t v 5 6 . 1 =t a c 5 2 =4 5 ? f b d 3 b d 3 ? h t d i w d n a b 9 t i u c r i c t s e t e e sv c c v 5 . 5 o t v 5 6 . 1 =t a c 5 2 =0 5 2z h m switch and ac characteristics notes: 9. guaranteed by design. 10. guaranteed by design but not production tested. the device contributes no other propagation delay other than the rc delay of the switch on resistance and the 50pf load capacitance, whne driven by an ideal voltage source with zero output impedance. 11. off isolation = 20 log 10 [ v a / v bn ] and is measured in db. 12. t a = 25c, f = 1mhz. capacitance is characterized but not tested in production.
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 5 ps8552d 02/24/05 pi5a3157 sot iny tm low voltage spdt analog switch 2:1 mux/demux bus switch 100 ? c l 10pf notes: input driven by 50w source terminated in 50 ? . c l includes load and stray capacitance. input prr = 1.0 mhz; t w = 500ns. from output under test figure 1. ac test circuit figure 2. ac waveforms figure 3. break before make interval timing test circuits and timing diagrams t r = 2.5ns 10% 10% 10% 10% 50% v cc v cc v ol +0.3v v oh ?0.3v v ol v oh v tri v tri v oh t w t plh t phl v ol gnd gnd 90% 50% 50% 50% 90% 50% 90% 90% 50% 50% 50% t r = 2.5ns t r = 2.5ns t r = 2.5ns t pzl t pzh t phz t plz switch input output control input output output c l r l t d v out 0.9 x v out logic input a a b 0 b 1 v in logic input v out
6 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi5a3157 sot iny tm low voltage spdt analog switch 2:1 mux/demux bus switch ps8552d 02/24/05 figure 4. charge injection test figure 5. off isolation figure 6. crosstalk figure 7. channel off capacitance figure 8. channel on capacitance c l r l 1m ? 100pf a s b n v ge r gen logic input logic input q = ( ? v out )(c l ) v out off on off ? v out analyzer a s 10nf gnd b n v cc v cc logic input 0v or b ih 50 ? 50 ? analyzer signal generator 0dbm s a 10nf gnd b 0 b 1 v cc v cc 50 ? 50 ? capacitance meter a s 10nf gnd f = 1 mhz b n v cc v cc logic input 0v or b ih capacitance meter a s 10nf gnd b n v cc v cc f = 1 mhz logic input 0v or b ih
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 7 ps8552d 02/24/05 pi5a3157 sot iny tm low voltage spdt analog switch 2:1 mux/demux bus switch figure 9. bandwidth 5 64 2 13 packaging mechanical: 6-pin sc70 (c) signal generator 0dbm a 10nf gnd b n logic input 0v or v cc s v cc v cc 50 ?
8 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi5a3157 sot iny tm low voltage spdt analog switch 2:1 mux/demux bus switch ps8552d 02/24/05 pericom semiconductor corporation 1-800-435-2336 www.pericom.com ordering information 0.0 - 0.05 1.50 0.10 1.00 0.10 0.23 0.05 (6x) 1.00 0.50 typ. 0.13 0.30 0.10 (6x) 0.1 x 45 ? chamfer pin 1 bottom view side views top view 0.80 max 0.80 max packaging mechanical: 6-pin tdfn (za) notes: 1. thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. x = tape and reel ordering code package code package description top marking pi5a3157cx c 6-pin sc70 zm pi5a3157cex c pb-free & green 6-pin sc70 zm PI5A3157ZAEX za pb-free & green 6-contact tdfn zm
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